EMC Trigger Path (Revised 28-Mar-03, A. VanderMolen)

• Tower Digitizer
• 12 Bit ADC value is produced for each tower
• The 10 top bits of each tower are sent with 15 others to a FPGA
• The top 8 bits of each tower are summed to create a 12 bit sum
• This 12 bit sum is passed through a Lookup Table to produce 6 bits of Trigger Patch
• Additionally the highest tower in each Patch is determined and then a user selectable six bits of this tower are used for High tower (Any consecutive 6 bits). Top bit is TRUE if it or any higher bits are TRUE.
• 300 pairs of these six bit values are sent to TDSMIs (Level 0 Trigger)
• Level 0 Trigger First Layer
• 10 Pairs of High Tower and Trigger Patch for input in each of 30 DSMs
• High Tower compared to each of three ordered levels. Output is 0,1,2(2 bits)
• Trigger Patch compared to each of three ordered levels. Output is 0,1,2(2 bits)
• A High tower to Trigger tower Ratio is produced-Not implemented
• The Ratio compared to each of three ordered levels. Output is 0,1,2(2 bits) -Not implemented
• A (one whole or two halves ) 10 bit Energy Sum is produced from the Trigger Patches.
• (1 or 2) 16 bits are send to layer two
• Level 0 Trigger Second Layer
• Five 16 bit inputs from layer one
• High tower, trigger tower, (ratio) bits “Ored” respectively to produces 6 bits.
• Jet patched produced
• The Jet patch compared to each of three ordered levels. Output is 0,1,2(2 bits)
• 8 bit Energy Sum is produced from the Jet patches.
• 16 bits are send to layer three
• Level 0 Trigger Third Layer
• Six 16 bit inputs from layer one
• High tower, trigger tower, (ratio) bits “Ored” respectively to produces 6 bits.
• Energy patched produced
• The Energy patch compared to each of three ordered levels. Output is 0,1,2(2 bits)
• Output experimentally defined